Informatics Publishing Limited

S. Ramasamy ¹, B. Venkataramani ²

Affiliations
1 Department of Electrical and Computer Engineering, Addis Ababa Science and Technology University, IN
2 Department of Electrical and Communication Engineering, National Institute of Technology, Tiruchirappalli, IN

Abstract

In this paper, an inverter based transconductor using double CMOS pair is proposed for implementation of a programmable bandpass filter suitable for Digital Radio Mondiale (DRM). Major contributions of this paper are: proposal for operating the transconductance (Gm) stage in sub-threshold region in order to minimize the power dissipation, proposal for switching in different Gm cells with suitable dummy stages for varying the centre frequency (F-tuning) and filter pass band (Q-tuning), proposal for a digital tuning technique for the filter based on phase comparison method for PVT compensation. The filter circuit is based on a biquad Gm-C topology, which is designed and implemented on CMOS 0.18μm technology with 1.8V supply using gm/Id design methodology. The post layout simulation results demonstrate the tunability of the centre frequency from 2MHz to 11MHz with quality factor tunable up to 50, which meets the requirements of DRM (upto 30MHz). Post layout simulation results show that the filter exhibits an in-band dynamic range of 53dB at gain of 7dB. An input IP3 of up to 28dBVp is achieved for an input signal of 100mVp. The SFDR over the entire bandwidth is 57dB. These features are obtained for a total power consumption of less than 300 μW from a single 1.8 V power supply with an estimated silicon area of 0.3mm². The proposed approach guarantees the upper bound on THD to be -40dB for 300mV_pp signal swing. The use of inverters with double CMOS pair results in 34dB higher PSRR compared to those using push pull inverter.

Keywords

Continuous Time Filter, Sub-Threshold, Intermediate Frequency (IF) Bandpass Filter, Double CMOS Pair.

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